1. FIELD OF THE INVENTION
This invention relates to a line equalizer and, particularly, to a line equalizer suitable for use in a digital transmission system in which the precursor appearing before one time slot T (T=l/f.sub.b, where f.sub.b is data transmission frequency) of the main pulse is pronounced due to distortion.
2. DESCRIPTION OF THE RELATED ART
In a system implementing digital transmission at a symbol rate of 100 kb/s or higher using a usual pair cable, a .sqroot.f equalizer having characteristics opposite to the pair cable is installed. However, due to the disparity of lines and the presence of bridged taps (open-ended branch lines), the waveform is distorted, and the intersymbol interference arises at the front and end of the most desirable decision instance (usually, the time point when the response waveform is maximum). The intersymbol interference after the decision instance is compensated by means of a conventional equalizer, e.g., automatic dicision feedback equalizer.
As a precursor equalizer for nullifying the precursor which is an interference component arising before the decision instance, especially before the time slot, there is known an equalizer which yields an equalized waveform without precursor through the process of retarding the input signal by one time slot T of the digital signal and adding the signal to the input signal which is inverted and amplified to the extent equal to the degree of the precursor. (Refer to IEEE, ISSCC Proc. 1985, p. 150 and IEEE, Journal of Solid-State Circuits, Vol. SC=17, No. 6, Dec. 1982, pp. 1045-1054).
The above-mentioned conventional equalizer for eliminating the precursor necessitates an analog delay line, polarity inverting circuit and analog multiplier, resulting in an increased manufacturing cost when it is intended to fabricate on LSI basis, and yet provides unsatisfactory characteristics.